Currently I`m working on a project which aims to accelerate virtual network functions with FPGA. I`ve been waiting for months but still haven`t got the high-end FPGA our lab purchased last year. Therefore, my fella I`ve been working together bought a relatively low-end fpga, SPARTAN-6, so that we can carry on with the research.
See, the trend of heterogeneous computing is moving towards OpenCL which has numerous advantages, such as familiar development experience among others, that can facilitate our research. Unfortunately, the fpga board we now have doesn`t support OpenCL which leaves us with no course but to code in Verilog. Although I`ve worked on Verilog for a while to develop an E-piano based on fpga with an external keyboard, conducting the research project is another league. So recently I`m learning how to do network programming with Verilog.
For starters, I need to get familiar with RGMII.
RGMII
Reduced Gigabit Media-Independent Interface is the interface that connects fast ethernet MAC to a PHY chip. RGMII PHY and a VSC8601 chip are integrated in the Spartan-6 fpga board. Sending/Receiving datastreams using RGMII is not that hard once we know the rules that have to be followed. The interface is programmable which means we`re presented with a lot of choices regarding the data transmission/receiving. Here I`m going to talk about the DDR mode.
DDR stands for double data rate. Implement this function is simple. By instantiating the primitive of IDDR2/ODDR2, we can set the right parameters so that the data would be transeived at DDR mode. Also, the robustness of the data transmission could be tested by a test program which sends data from 1 to 255 repeatedly.
